1. Field of the Invention
The present invention relates to a bus bandwidth monitoring device and a bus bandwidth monitoring method.
Priority is claimed on Japanese Patent Application No. 2010-181610, filed Aug. 16, 2010, the content of which is incorporated herein by reference.
2. Description of the Related Art
All patents, patent applications, patent publications, scientific articles, and the like, which will hereinafter be cited or identified in the present application, will hereby be incorporated by reference in their entirety in order to describe more fully the state of the art to which the present invention pertains.
In many of the system LSIs, for example, system LSIs mounted in image processing devices such as a camera for static images, a camera for dynamic images, an endoscope for medical use, and an endoscope for industrial use, a plurality of built-in processing blocks share a single DRAM (Dynamic Random Access Memory) connected thereto. In such system LSIs, the built-in processing blocks are connected to a data bus inside the system LSI. Each processing block accesses the DRAM through DMA (Direct Memory Access). At this time, a bus controller controls accesses to the DRAM while properly arbitrating requests to access the DRAM from the processing blocks. In the arbitration of the access requests by the bus controller, it is required that the access requests from the processing blocks be arbitrated so as to satisfy the performance as a system.
Methods of arbitrating access requests include the static priority method and the round-robin method. The static priority method is a method in which a static level of priority is preset for every processing block and the access request from the processing block with a higher level of priority is preferentially accepted. In the round-robin method, the processing block whose access request has been accepted is set lower in its level of priority while the processing block whose access request has not been accepted is set higher in its level of priority, thus making the access requests from the processing blocks equally acceptable.
However, the methods of arbitrating access requests such as the static priority method and the round-robin method is not capable of finely set the priority levels of the processing blocks according to, for example, operation modes of the image processing apparatus. For example, Japanese Unexamined Patent Application, First Publication No. H5-61818 discloses a technique of counting the number of times the access request is accepted in every processing block, and then changing the priority levels of the processing blocks based on the count.
With the combination of the static priority method and the round-robin method, for example, Japanese Unexamined Patent Application, First Publication No. 2007-114918 and Japanese Unexamined Patent Application, First Publication No. 2004-178056 discloses a method of dynamically arbitraging access requests in which the priority levels of the processing block are dynamically modified. In the technique disclosed in Japanese Unexamined Patent Application, First Publication No. 2007-114918, the priority levels of the processing blocks are dynamically changed according to the frequency of the access requests sent from the processing blocks such as by making higher the priority levels of the processing blocks whose access request has not been accepted for a predetermined period of time or longer. In the technique disclosed in Japanese Unexamined Patent Application, First Publication No. 2004-178056, priority levels of a plurality of processing blocks are incremented by a predetermined amount when the access requests from the processing blocks conflict one another, to thereby modify the priority levels dynamically.
In a method of arbitrating access requests such as disclosed in Japanese Unexamined Patent Application, First Publication No. H5-61818, the number of access requests of each processing block within a predetermined time for measurement range. Thereby, an average value of the bus bandwidths, which represents data amounts on the data bus when DRAM is accessed by each processing block, (an average bandwidth) is measured. Based on the information on the measured average bandwidth, the priority level of each processing block is changed.
However, in the actual operation of each processing block, there are cases where a variance in frequency of access requests results in a longer processing time or an excessive occupation of the data bus even if the average bandwidth of the data bus is the same.
A relationship among the frequency of an access request, the processing time, and the occupation of a data bus will be described. FIG. 7 schematically shows an exemplary relationship between accesses and processing time of a single processing block. FIG. 7 shows the case of a processing block in which an internal processing is performed for every set of two bus accesses. FIG. 7(a) shows an example in which the grouped bus accesses causes an occupation of access to a DRAM for a certain length of time. FIG. 7(b) shows an example in which the bus accesses to the DRAM is not grouped but dispersed. The measurement result of the average bandwidth of the data bus is the same for the bus accesses shown in FIG. 7(a) and the bus accesses shown in FIG. 7(b). In the case of FIG. 7(a), it is possible to occupy the accesses to the DRAM. However, because data for the subsequent processing is not prepared after completion of the internal processing, the time in which the internal processing is suspended is long, resulting in a long processing time.
FIG. 8 schematically shows an exemplary relationship of accesses of a data bus in two processing blocks. Similarly to FIG. 7, FIG. 8 shows the case of a processing block in which an internal processing is performed for every set of two bus accesses. FIG. 8(a) shows an exemplary relationship between bus accesses and a processing time in the case where bus accesses of a single processing block are made in a grouped manner, similarly to FIG. 7(a). FIG. 8(b) shows an exemplary relationship between bus accesses and a processing time in the case where bus accesses of a single processing block are made in a dispersed manner, similarly to FIG. 7(b). Similarly to FIG. 7, the measurement result of the average bandwidth of the data bus is the same for FIGS. 8(a) and 8(b). In addition, unlike FIGS. 7(a) and 7(b), the processing time of the processing block is the same for FIGS. 8(a) and 8(b).
FIGS. 8(c) and 8(d) show cases where two processing blocks are in simultaneous operation. FIG. 8(e) shows a case where a processing block A, which makes bus accesses in a grouped manner similarly to FIG. 8(a), and a processing block B, which makes bus accesses in a dispersed manner similarly to FIG. 8(b), are in simultaneous operation. FIG. 8(d) shows a case where a processing block A and a processing block B, which make bus accesses in a dispersed manner similarly to FIG. 8(b), are in simultaneous operation.
As is seen from FIGS. 8(c) and 8(d), simultaneous operation of two processing blocks produces a difference in the entire processing time even if the average bandwidth and the processing time are the same in one of the processing blocks, that is, the processing block A. Namely, in FIG. 8(d), two processing blocks are capable of accessing DRAM without interfering each other. On the other hand, in FIG. 8(c), conflicts in the data bus in periods X produce periods of time that prevents the processing block B from accessing the DRAM, resulting in at long, entire processing time. The conflicts in the data bus in the periods X were produced by the occupation of the access to the DRAM by the processing block A when the processing block B is to access the DRAM.
Thus, only by the average bandwidth when the processing blocks use the data bus, it is not possible to judge the performance as a system. Therefore, it is difficult to properly arbitrate the access requests from the processing blocks.
In the techniques of dynamically modifying the priority levels such as disclosed in Japanese Unexamined Patent Application, First Publication No. 2007-114918 and Japanese Unexamined Patent Application, First Publication No. 2004-178056, it is often required to set the priority levels of the processing blocks according to the average bandwidth of the data bus in the access requests sent from the processing blocks, the capacities of the buffers provided in the processing blocks, the importance levels of the processing blocks in each operation mode of the system, and the like, so as not to cause a failure as a system.
However, there is no way to obtain information functioning as a guideline when the priority levels of the processing blocks are set. For example, if there is a failure as a system, there is no way to identify factors such as which processing block has caused the system failure or the degree of modification of the priority settings to allow the system to operate without failure. Therefore, conventionally, in setting the priority levels of the processing blocks, the priority levels are provisionally set and the system is actually operated. With the repetition of this procedure, the settings that do not cause a failure as a system are found. This results in a low efficiency in system development.